Verilog Project

ECE5623/4623 Synchronization, Edge Detection, State Machine, LFSR Fitzmorris
Part 1, Signal Synchronization:
Whenever a signal from another clock domain enters our circuit, it needs to be synchronized to avoid
the possibility of metastability arising from a setup/hold timing violation. The best way to synchronize
the incoming signal is with a synchronization chain as shown in Figure 3 in the document labeled
“Metastability, Clock Domain Crossing” which can be found in the Technical Document module of
Canvas.
Write a module in Verilog that has two inputs (Clk and Data) and one output (Sdata). Data is the input
data for the synchronization chain, Clk is the clock we’re synchronizing the data to (in our case
CLOCK_50), and Sdata is the synchronized data. The synchronization chain should include three flip‐flops
as opposed to the two sown in Figure 3.
Use ModelSim to perform a simulation of your circuit. Write a testbench to generate data for Data and
Clk. Take a screenshot of your simulation results showing the three‐cycle delay between Data and Sdata.
Upload the Verilog code for your synchronizer and testbench in .v format. Upload the screenshot of your
simulation results.
Save this module in a place where you can find it because we’ll be using it in later designs.
Part 2, Edge Detection:
Signals generated by slow processes such as mechanical switches or sensors may have pulse widths that
last for many clock cycles. Often, we want to generate a single pulse when the slow signal transitions
from low to high (rising edge) or from high to low (falling edge).
The circuit shown in Figure 12‐3 in the document “Altera Design Practices” can be used to detect the
rising edge of a slow input signal. The circuit can be easily modified to detect a falling edge. The
document “Altera Design Practices” can be found in the Technical Documents module on Canvas.
Write the Verilog code for a module that will detect both rising and falling edges of an input signal. The
module should have one input (Data) and two outputs (Rise and Fall). Rise should be high for one clock
cycle when Data rises from low to high and Fall should be high for one clock cycle when Data falls from
high to low. Both Rise and Fall should be 0 otherwise.
Perform a simulation using Modelsim that shows CLOCK_50, Data, Rise, and Fall. Use a testbench to
generate data for the input Data that will cause two pulses each on Rise and Fall. Take a screenshot of
your simulation showing the two pulses.
Upload your Verilog code for both the edge detector and the testbench in .v format. Upload your
screenshot of the simulation results.
Save this module in a place where you can find it because we’ll be using it in later designs.

ECE5623/4623 Synchronization, Edge Detection, State Machine, LFSR Fitzmorris
Part 3, State Machine:
State machines are useful to generate signals in a specific pattern and can change the pattern based on
inputs to the state machine. The diagram below describes a state machine that can be used to drive a
stepper motor.
The input Dir determines the direction of the motor by determining the order of the outputs. The four‐
bit output for each state is shown within the state bubble after the slash. For example, when the state
machine is in state S1, the four‐bit output should be 0110. If Dir = 1, the machine should move to S2 on
the next clock cycle and the correct output should be 1010.
You can find many tutorials covering state machines in Verilog and here’s one that I found useful:
https://digilent.com/blog/how‐to‐code‐a‐state‐machine‐in‐verilog/
Write a Verilog module that implements the state machine shown above. Your state machine should
transition from state to state once per second (note: you can use the 1Hz “slow counter” technique
from previous exercises to do this). For the input Dir, use SW[0]. Display the output bits on LEDR[9:6].
ECE5623/4623 Synchronization, Edge Detection, State Machine, LFSR Fitzmorris
Upload the Verilog code for your module in .v format. In the comment section of your submission, put a
link to a video of your circuit working. Make sure to demonstrate a full cycle of outputs with Dir at 0 and
then again with Dir at 1.
Part 4, Linear Feedback Shift Register (LFSR), ECE5623 Only:
Linear Feedback Shift Registers are extremely important in the fields of cryptography, error‐detection,
and test pattern generation. Many descriptions of LFSRs can be found and here is a good starting point:
https://en.wikipedia.org/wiki/Linear‐feedback_shift_register
Read the section of Fibonacci LFSRs until you understand how they operate.
Write a Verilog module that implements a 5‐bit Fibonacci LFSR with taps in positions 5 and 3 (note that
the figure below is a 16‐bit LFSR with taps in positions 16, 14, 13, and 11 so you’ll need to adapt the
figure to suit your needs). Instead of XOR, use XNOR so the “stuck state” or “invalid state” is all 1’s
instead of all 0’s.
Your LFSR should include a reset input that will set all five bits in the register to 0 when the reset signal
is high.
Simulate your circuit using ModelSim. Write a testbench to provide a 50MHz clock and to display the
contents of the register in hex. Take a screenshot of your simulation outputs with 31 consecutive
outputs starting from 00000 (right after a reset). Verify that the hex numbers are visible and readable on
the screenshot.
Upload the Verilog code for your LFSR and your testbench in .v format. Upload the screenshot of your
simulation results.
Late Policy:
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